VL7202 LOW POWER VLSI DESIGN

VL7202 LOW POWER VLSI DESIGN

UNIT I           POWER DISSIPATION

Hierarchy of limits of power – Sources of power consumption – Physics of power dissipation in CMOS FET devices – Basic principle of low power design. 

UNIT II         POWER OPTIMIZATION

Logic level power optimization – Circuit level low power design – circuit techniques for reducing power consumption in adders and multipliers

UNIT III       DESIGN OF LOW POWER CIRCUITS

Computer arithmetic techniques for low power system – reducing power consumption in memories – low power clock, Inter connect and layout design – Advanced techniques –Special techniques. 

UNIT IV       POWER ESTIMATION

Power Estimation technique – logic power estimation – Simulation power analysis –Probabilistic power analysis. 

UNIT V       SYNTHESIS AND SOFTWARE DESIGN

Synthesis for low power – Behavioral level transform – software design for low power. 

REFERENCES: 

1. Kaushik Roy and S.C.Prasad, “Low power CMOS VLSI circuit design”, Wiley, 2000. 

2. Dimitrios Soudris, Christians Pignet, Costas Goutis, “Designing CMOS Circuits for Low Power”, Kluwer, 2002. 

3. J.B.Kulo and J.H Lou, “Low voltage CMOS VLSI Circuits”, Wiley 1999. 

4. A.P.Chandrasekaran and R.W.Broadersen, “Low power digital CMOS design”, Kluwer,1995. 

5. Gary Yeap, “Practical low power digital VLSI design”, Kluwer, 1998. 

6.  Abdelatif Belaouar, Mohamed.I.Elmasry, “Low power digital VLSI design”, Kluwer, 1995. 

7. James B.Kulo, Shih-Chia Lin, “Low voltage SOI CMOS VLSI devices and Circuits”, John Wiley and sons, inc. 2001. 

8. Steven M.Rubin, “Computer Aids for VLSI Design”, Addison Wesley Publishing