VL7001 ANALOG AND MIXED MODE VLSI DESIGN

VL7001 ANALOG AND MIXED MODE VLSI DESIGN

UNIT I INTRODUCTION AND BASIC MOS DEVICES

Challenges in analog design-Mixed signal layout issues- MOS FET structures and characteristicslarge signal model – small signal model- single stage Amplifier-Source follower- Common gate stage – Cascode Stage 

UNIT II SIBMICRON CIRCUIT DESIGN

Submicron CMOS process flow, Capacitors and resistors, Current mirrors, Digital Circuit Design, Delay Elements – Adders- OP Amp parameters and Design 

UNIT III DATA CONVERTERS

Characteristics of Sample and Hold- Digital to Analog Converters- architecture-Differential Non linearity-Integral Non linearity- Voltage Scaling-Cyclic DAC-Pipeline DAC-Analog to Digital Converters- architecture – Flash ADC-Pipeline ADC-Differential Non linearity-Integral Non linearity 

UNIT IV SNR IN DATA CONVERTERS

Overview of SNR of Data Converters- Clock Jitters- Improving Using Averaging – Decimating Filters for ADC- Band pass and High Pass Sinc Filters- Interpolating Filters for DAC

UNIT V   SWITCHED CAPACITOR CIRCUITS

Resistors, First order low pass Circuit, Switched capacitor Amplifier,Switched Capacitor Integrator. 

REFERENCES: 

1. Vineetha P.Gejji Analog and Mixed Mode Design- Prentice Hall, 1st Edition , 2011 

2. JeyaGowri Analog and Mixed Mode Design- Sapna publishing House 2011