AP7016 SYSTEM ON CHIP DESIGN

AP7016 SYSTEM ON CHIP DESIGN

UNIT I LOGIC GATES

Introduction. Combinational Logic Functions. Static Complementary Gates. Switch Logic. Alternative Gate Circuits. Low-Power Gates. Delay Through Resistive Interconnect. Delay Through Inductive Interconnect. 

UNIT II COMBINATIONAL LOGIC NETWORKS

Introduction. Standard Cell-Based Layout. Simulation. Combinational Network Delay. Logic and interconnect Design. Power Optimization. Switch Logic Networks. Combinational Logic Testing. 

UNIT III SEQUENTIAL MACHINES

Introduction. Latches and Flip-Flops. Sequential Systems and Clocking Disciplines. Sequential System Design. Power Optimization. Design Validation. Sequential Testing. 

UNIT IV SUBSYSTEM DESIGN

Introduction. Subsystem Design Principles. Combinational Shifters. Adders. ALUs. Multipliers. HighDensity Memory. FieldProgrammable Gate Arrays. Programmable Logic Arrays. References. Problems. 

UNIT V FLOOR-PLANNING

Introduction, Floor-planning Methods – Block Placement & Channel Definition, Global Routing, switchbox Routing, Power Distribution, Clock Distributions, Floor-planning Tips, Design Validation. Off-Chip Connections –Packages, The I/O Architecture, PAD Design. T

REFERENCES: 

1. WayneWolf, “Modern VLSI Design – System –on – Chip Design”, Prentice Hall, 3rd Edition 2008. 

2. WayneWolf, “Modern VLSI Design – IP based Design”, Prentice Hall, 4th Edition , 2008.