VL7101 VLSI SIGNAL PROCESSING

VL7101 VLSI SIGNAL PROCESSING

UNIT I INTRODUCTION 6 Overview of DSP – FPGA Technology – DSP Technology requirements – Design Implementation.

UNIT II METHODS OF CRITICAL PATH REDUCTION

Binary Adders – Binary Multipliers – Multiply-Accumulator (MAC) and sum of product (SOP) – Pipelining and parallel processing – retiming – unfolding – systolic architecture design. 

UNIT III     ALGORITHMIC STRENGTH REDUCTION METHODS AND RECURSIVE FILTER DESIGN

Fast convolution-pipelined and parallel processing of recursive and adaptive filters – fast IIR filters design. 

UNIT IV DESIGN OF PIPELINED DIGITAL FILTERS

Designing FIR filters – Digital lattice filter structures – bit level arithmetic architecture – redundant arithmetic – scaling and round-off noise. 

UNIT V SYNCHRONOUS ASYNCHRONOUS PIPELINING AND PROGRAMMABLE DSP

Numeric strength reduction – synchronous – wave and asynchronous pipelines – low power design – programmable DSPs – DSP architectural features/alternatives for high performance and low power.

REFERENCES: 

1. Keshab K.Parhi, “VLSI Digital Signal Processing Systems, Design and Implementation”, John Wiley, Indian Reprint, 2007. 

2. U. Meyer – Baese, "Digital Signal Processing with Field Programmable Arrays", Springer, Second Edition, Indian Reprint, 2007. 

3. S.Y.Kuang, H.J. White house, T. Kailath, “VLSI and Modern Signal Processing”, Prentice Hall, 1995.