ET7201 VLSI ARCHITECTURE AND DESIGN METHODOLOGIES

ET7201   VLSI ARCHITECTURE AND DESIGN METHODOLOGIES              

UNIT I     CMOS DESIGN

Overview of digital VLSI design Methodologies- Logic design with CMOS-transmission gate circuits-Clocked CMOS-dynamic CMOS circuits, Bi-CMOS circuits- Layout diagram, Stick diagram-IC fabrications – Trends in IC technology.

UNIT II   PROGRAMABLE  LOGIC DEVICES

 Programming Techniques-Anti fuse-SRAM-EPROM and EEPROM technology – ReProgrammable Devices Architecture- Function blocks, I/O blocks,Interconnects, Xilinx- XC9500,Cool  Runner - XC-4000,XC5200, SPARTAN, Virtex - Altera MAX 7000-Flex 10KStratix. 

UNIT III  BASIC CONSTRUCTION, FLOOR PLANNING, PLACEMENT AND   ROUTING

System partition – FPGA partitioning – Partitioning methods- floor planning – placement- physical design flow – global routing – detailed routing – special routing- circuit extraction – DRC. 

UNIT IV  ANALOG VLSI DESIGN

Introduction to analog VLSI- Design of  CMOS 2stage-3 stage Op-Amp –High Speed and High frequency op-amps-Super MOS-Analog primitive cells-realization of neural networks.

UNIT V    LOGIC SYNTHESIS AND SIMULATION

Overview of digital design with Verilog HDL, hierarchical modelling concepts, modules and port definitions, gate level modelling, data flow modelling, behavioural modelling, task & functions, Verilog and logic synthesis-simulation-Design examples,Ripple carry Adders, Carry Look ahead adders, Multiplier, ALU, Shift Registers, Multiplexer, Comparator, Test Bench.    

                      

REFERENCES: 

1. M.J.S Smith, “Application Specific integrated circuits”,Addition Wesley Longman     Inc.1997. 2.Kamran Eshraghian,Douglas A.pucknell and Sholeh Eshraghian,”Essentials of VLSI     circuits and system”, Prentice Hall India,2005. 

3. Wayne Wolf, “ Modern VLSI design “ Prentice Hall India,2006. 

4. Mohamed Ismail ,Terri Fiez, “Analog VLSI Signal and information Processing”,      McGraw Hill International Editions,1994. 

5.Samir Palnitkar, “Veri Log HDL, A Design guide to Digital and Synthesis” 2nd     Ed,Pearson,2005. 

6. John  P. Uyemera “Chip design for submicron VLSI cmos layout and simulation “, Cengage     Learning India Edition”, 2011.