AP7001 COMPUTER ARCHITECTURE AND PARALLEL PROCESSING
UNIT I COMPUTER DESIGN AND PERFORMANCE MEASURES
Fundamentals of Computer Design– Parallel and Scalable Architectures – Multiprocessors – Multivector and SIMD architectures–Multithreaded architectures–Data-flow architectures-Performance Measures
UNIT II PARALLEL PROCESSING, PIPELINING AND ILP
Instruction Level Parallelism and Its Exploitation- Concepts and Challenges - Overcoming Data Hazards with Dynamic Scheduling – Dynamic Branch Prediction - Speculation - Multiple Issue Processors Performance and Efficiency in Advanced Multiple Issue Processors
UNIT III MEMORY HIERARCHY DESIGN
Memory Hierarchy - Memory Technology and Optimizations – Cache memory – Optimizations of Cache Performance–Memory Protection and Virtual Memory-Design of Memory Hierarchies
UNIT IV MULTIPROCESSORS 9 Symmetric and distributed shared memory architectures – Cache coherence issues - Performance Issues – Synchronization issues – Models of Memory Consistency - Interconnection networks – Buses, crossbar and multi-stage switches.
UNIT V MULTI-CORE ARCHITECTURES
Software and hardware multithreading – SMT and CMP architectures – Design issues – Case studies – Intel Multi-core architecture–SUN CMP architecture–IBM cell architecture-hp architecture.
REFERENCES:
1. Kai Hwang, "Advanced Computer Architecture", McGraw Hill International, 2001.
2. John L. Hennessey and David A. Patterson, “Computer Architecture – A quantitative approach”, Morgan Kaufmann / Elsevier, 4th. edition, 2007.
3. William Stallings, “Computer Organization and Architecture – Designing for Performance”, Pearson Education, Seventh Edition, 2006.
4. John P. Hayes, “Computer Architecture and Organization”, McGraw Hill
5. David E. Culler, Jaswinder Pal Singh, “Parallel Computing Architecture: A hardware/ software approach”, Morgan Kaufmann / Elsevier, 1997.
6. Dimitrios Soudris, Axel Jantsch, "Scalable Multi-core Architectures: Design Methodologies and Tools", Springer, 2012
7. John P. Shen, “Modern processor design. Fundamentals of super scalar processors”, Tata McGraw Hill 2003.
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