AP7010 DATA CONVERTERS

AP7010 DATA CONVERTERS

UNIT I SAMPLE AND HOLD CIRCUITS

Sampling switches, Conventional open loop and closed loop sample and hold architecture, Open loop architecture with miller compensation, multiplexed input architectures, recycling architecture switched capacitorarchitecture. 

UNIT II SWITCHED CAPACITOR CIRCUITS AND COMPARATORS

Switched-capacitor amplifiers, switched capacitor integrator, switched capacitor common mode feedback. Single stage amplifier as comparator, cascaded amplifier stages as comparator, latched comparators.

UNIT III DIGITAL TO ANALOG CONVERSION

Performance metrics, reference multiplication and division, switching and logic functions in DAC, Resistor ladder DAC architecture, current steering DAC architecture. 

UNIT IV ANALOG TO DIGITAL CONVERSION

Performance metric, Flash architecture, Pipelined Architecture, Successive approximation architecture, Time interleaved architecture. 

UNIT V PRECISION TECHNIQUES

Comparator offset cancellation, Op Amp offset cancellation, Calibration techniques, range overlap and digital correction. 

REFERENCE: 1. Behzad Razavi, “Principles of data conversion system design”, S. Chand and company Ltd, 2000.