CS9211 COMPUTER ARCHITECTURE Question Paper

M.E/M.Tech DEGREE EXAMINATION, JANUARY 2010

First Semester

Computer Science and Engineering

CS9211 – COMPUTER ARCHITECTURE

(Common to M.Tech - Information Technology)

(Regulation 2009)

Time: Three hours Maximum: 100 Marks

Answer all the questions

Part A – (10*2=20 Marks)

1. What is hazard? State its types.
2. Mention the techniques available to measure the performance.
3. What is dynamic scheduling?
4. Give the limitation of ILP.
5. Distinguish between hardware and software speculation mechanisms.
6. What is static branch prediction?
7. What are the synchronization issues?
8. What is multithreading?
9. Define cache miss penalty?
10. What is RAID?

Part B – (5*16 = 80 Marks)

11. (a)How does one classify ISA? Discuss their design issues. (16)

(Or)

(b)What is pipelining? Explain various hazards involved in implementing pipelining. (16)
12. (a)Explain the instruction level parallelism with dynamic approaches. (16)

(Or)

(b)What is dynamic hardware prediction? Explain it in detail. (16)
13. (a)Explain the different hardware support for exposing ILP. (16)

(Or)

(b)Explain the different hardware support for more parallelism. (16)
14. (a)Explain distributed shared memory architecture with necessary life cycle diagram. (16)

(Or)

(b)(i)Differentiate software and hardware multithreading approaches. (8)
(ii)Explain the models of memory consistency. (8)
15. (a)How does one reduce cache miss penalty and miss rate? Explain. (16)

(Or)

(b)What are the ways available to measure the I/O performance? Explain each of them in detail. (16)

M.E/M.Tech DEGREE EXAMINATION, JUNE 2010

First Semester

Computer Science and Engineering

CS9211 – COMPUTER ARCHITECTURE

(Common to M.Tech - Information Technology)

(Regulation 2009)

Time: Three hours Maximum: 100 Marks

Answer all the questions

Part A – (10*2=20 Marks)

1. State the principle of locality and its types.
2. What are the choices for encoding instruction set.
3. What is speculation? Give an example.
4. Mention the effects of imperfect alias analysis.
5. What is loop unrolling?
6. Give the uses of sentinel.
7. Define multiprocessor cache coherence.
8. What are the approaches used for multithreading?
9. Which block should be replaced on a cache Miss?
10. How is cache performance improved?

Part B – (5*16=80 Marks)

11. (a)(i)Explain the operations designed for media and signal processing. (10)
(ii)Explain the ways in which a computer architect can help the compiler writer. (6)

(Or)

(b)(i)Discuss the addressing modes used for signal processing instructions. (7)
(ii)Describe the addressing modes and instructions designed for control flow. (9)
12. (a)Explain the techniques to overcome data hazards with dynamic scheduling. (16)

(Or)

(b)Describe the limitations of Instruction level Parallelism. (16)
13. (a)(i)Explain the basic VLIW approach used for static multiple issues. (8)
(ii)Enumerate the crosscutting issues in hardware and s/w speculation mechanisms. (8)

(Or)

(b)(i)Explain the hardware support for exposing more parallelism at compile time. (8)
(ii)Describe the basic compiler techniques for exposing ILP. (8)
14. (a)(i)Describe the design challenges in SMT processors. (8)
(ii)Discuss the performance of shared memory multiprocessors. (8)

(Or)

(b)(i)Explain synchronization mechanisms designed for large scale multiprocessors. (9)
(ii)Discuss the details of memory consistency models. (7)
15. (a)(i)Explain the concept of miss penalty and out of order execution in processors. (6)
(ii)Discuss the methods of interface between CPU and memory. (10)

(Or)

(b)Discuss in detail the different levels of RAID. (16)